The present invention relates generally to integrated circuit (IC) designs, and more particularly to an electrostatic discharge (ESD) protection circuit that has a layout view, in which a various number of transistor areas can be selectively arranged to adjust the parasitic capacitance of the ESD protection circuit.
The gate oxide of a metal-oxide-semiconductor (MOS) transistor of an IC is most susceptible to damage. The gate oxide may be destroyed by being contacted with a voltage only a few volts higher than the supply voltage. It is understood that a regular supply voltage in an IC is 5.0, 3.3 volt or even lower. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive even though the charge and any resulting current are extremely small. For this reason, it is of critical importance to discharge any electrostatic charge, before it accumulates to a damaging voltage.
An ESD protection circuit is typically added to an IC at the bond pads. The bond pads are connections allowing the IC to connect to outside circuitries, electric power supplies, electric grounds, and electronic signals. Such added ESD protection circuit must allow a normal operation of the IC. This means that the protection circuit is effectively isolated from the normally operating core circuitry of the IC because it blocks a current flow, through itself, to ground or any other circuits or pads. In an operating IC, electric power is supplied to a VCC pad, electric ground is supplied to a VSS pad, electronic signals are supplied from outside to one or more pads, and electronic signals generated by the core circuitry of the IC are supplied to other pads for delivery to external circuits and devices. In an isolated, unconnected IC, all pads are considered to be electrically floating, or of indeterminate voltage.
ESD can arrive at any pad. This can happen, for example, when a person touches some of the pads on the IC. This is the same static electricity that may be painfully experienced by a person who walks across a carpet on a dry day and then touches a grounded metal object. In an isolated IC, ESD acts as a brief power supply for one or more pads, while the other pads remain floating, or grounded. Because the other pads are grounded, when ESD acts as a power supply at a randomly selected pad, the protection circuit acts differently than it does when the IC is operating normally. When an ESD event occurs, the protection circuit must quickly become conductive so that the electrostatic charge is conducted to VSS or ground, and is thus dissipated before it damages the core circuitry.
An ESD protection circuit, therefore, has two states: a normal operation mode and an ESD mode. When an IC is in the normal operation mode, the ESD protection circuit appears invisible to the IC by blocking current through itself and thus has no effect on the core circuitry. In the ESD mode, the ESD protection circuit serves its purpose of protecting the core circuit by conducting an electrostatic charge quickly to VSS, or ground.
It has been found that a four layer PNPN device called a silicon controlled rectifiers (SCR) can be one of the most effective devices in an ESD protection circuits in preventing the ESD damage. A SCR operates in two modes: a blocking mode and a latch-up mode. In the blocking mode, the SCR blocks a current flow therethrough, such that the ESD protection circuit has no effect on the core circuitry to be protected. Where there is a sufficient regeneration of current flow in the SCR, the latch-up condition is created. This enables a large current to flow through the SCR, and therefore, bypass an ESD current from the core circuitry during an ESD event.
It is understood that adding an NMOS transistor to the ESD protection circuit helps lower the trigger voltage for latching up the SCR. When doing so, the size of the NMOS transistor needs to be carefully designed. On the one hand, the NMOS transistor may turn on earlier than the SCR, if its size is large enough. On the other hand, the NMOS transistor may not effectively reduce the trigger voltage of the SCR, if its size is too small. The larger the size of the NMOS transistor, the greater the parasitic capacitance it provides. As a result, the greater the parasitic capacitance, the lower the trigger voltage of the SCR.
As such, what is needed is an ESD protection circuit that utilizes an SCR with an adjustable parasitic capacitance to reduce the trigger voltage of the same for a faster response to an ESD event.